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| INTEGRATED CIRCUITS PDIUSBD12 USB interface device with parallel bus Product specification Supersedes data of 1998 Sep 24 1999 Jan 08 Philips Semiconductors Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 FEATURES * Complies with the Universal Serial Bus specification Rev. 1.1 * High performance USB interface device with integrated SIE, FIFO memory, transceiver and voltage regulator DESCRIPTION The PDIUSBD12 is a cost and feature-optimized USB device. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high speed general-purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution. The PDIUSBD12 fully conforms to the USB specification Rev. 1.1. It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices. As such, the PDIUSBD12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNOW, and USB power management requirements. The low operating power allows the implementation of bus-powered peripherals. In addition, it also incorporates features like SoftConnectTM, GoodLinkTM, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals. * Compliant with most Device Class specifications * High-speed (2 Mbytes/s) parallel interface to any external microcontroller/microprocessor * Fully autonomous DMA operation * Integrated 320 bytes of multi-configuration FIFO memory * Double buffering scheme for main endpoint increases throughput and eases real time data transfer * 1MByte/s data transfer rate achievable in Bulk mode, 1Mbit/s data transfer rate achievable in Isochronous mode * Bus-powered capability with very good EMI performance * Controllable LazyClock output during suspend * Software controllable connection to the USB bus (SoftConnectTM) * Good USB connection indicator that blinks with traffic (GoodLinkTM) * Programmable clock frequency output * Complies with the ACPI, OnNOW, and USB power management requirements * Internal power-on reset and low voltage reset circuit * Available in SO28 and TSSOP28 pin packages * Full industrial grade operation from -40 to +85C * Higher than 8kV in-circuit ESD protection lowers cost of extra components * Full-scan design with high fault coverage (>99%) ensures high quality * Operation with dual voltages: transfers 3.3 0.3V or extended 5V supply range of 3.6 - 5.5V * Multiple interrupt modes to facilitate both bulk and isochronous ORDERING INFORMATION PACKAGES 28-pin plastic SO 28-pin plastic TSSOP TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA PDIUSBD12 D PDIUSBD12 PW NORTH AMERICA PDIUSBD12 D PDUSBD12PW DH PKG. DWG. # SOT136-1 SOT361-1 1999 Jan 08 2 853-2110 20620 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 BLOCK DIAGRAM 6 MHz 3.3V 1.5kW D+ SoftConnectTM UPSTREAM PORT D+ D- PLL BIT CLOCK RECOVERY INTEGRATED RAM ANALOG TX/RX PHILIPS SIE MEMORY MANAGEMENT UNIT VOLTAGE REGULATOR PARALLEL AND DMA INTERFACE SV00859 NOTE: * This is a conceptual block diagram and does not include each individual signal. Analog Transceiver The integrated transceiver interfaces directly to the USB cables through termination resistors. SoftConnectTM The connection to the USB is accomplished by bringing D+ (for high-speed USB device) high through a 1.5 k pull-up resistor. In the PDIUSBD12, the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through EOT_N pin. See the pin description for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull up voltage for the normally open-drain output of the DMA controller pin. It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. The decision to make sure of this feature lies with the users. SoftConnectTM is a patent pending technology from Philips Semiconductors. Voltage Regulator A 3.3V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 k pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnectTM technology with integrated 1.5 k pull-up resistor. PLL A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL. Bit Clock Recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. 1999 Jan 08 3 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 GoodLinkTM Good USB connection indication is provided through GoodLinkTM technology. During enumeration, the LED indicator will blink ON momentarily corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be permanently ON. Subsequent successful (with acknowledgement) transfer to and from the PDIUSBD12 will blink OFF the LED. During suspend, the LED will be OFF. This feature provides a user-friendly indicator on the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty equipment. This feature helps lower field support and hotline costs. Parallel and DMA Interface A generic parallel interface is defined for ease-of-use, speed, and allows direct interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a memory device with 8-bit data bus and 1 address bit (occupying 2 locations). The PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The PDIUSBD12 also supports DMA (Direct Memory Access) transfer which allows the main endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both single cycle and burst mode DMA transfers are supported. Example of parallel interface to a dedicated 80C51 In this example, the ALE is permanently tied LOW to signify a separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to any of the 80C51 I/O port. This port controls command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be connected directly to the data bus of the PDIUSBD12. The address phase will simply be ignored by the PDIUSBD12. The crystal input of the 80C51 can be supplied by the CLKOUT output of the PDIUSBD12. Memory Management Unit (MMU) and Integrated RAM The MMU and the integrated RAM buffer the difference in speed between USB, running in bursts of 12 Mbits/s and the parallel interface to the microcontroller. This allows the microcontroller to read and write USB packets at its own speed. PDIUSBD12 80C51 INT_N A0 DATA [7:0] WR_N RD_N -INTO/P3.2 ANY I/O PORT (e.g. P3.3) P [0.7:0.0]/AD [7:0] -WR/P3.6 -RD/P3.7 CLKOUT XTAL1 CS_N ALE SV00870 1999 Jan 08 4 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 DMA TRANSFER Direct Memory Address (DMA) allows an efficient transfer of a block of data between the host and the local shared memory. Using a DMA controller, data transfer between the PDIUSBD12 main endpoint (endpoint 2) and the local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is setup for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single cycle DMA or burst mode DMA. In single cycle DMA, the DMREQ is deactivated for every single acknowledgement by the DMACK_N before being asserted again. In burst mode DMA, the DMREQ is held active for the number of bursts programmed in the device before returning inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation, the DMREQ will only be activated whenever the buffer is full signifying that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases effective throughput. For the case when the host does not fill up the buffer completely (less than 64 bytes or 128 bytes for single direction ISO configuration), the DMREQ will be deactivated at the last byte of the buffer regardless of the current DMA burst count. It will be asserted again on the next packet with a refreshed DMA burst count. Similarly, for DMA write operation, the DMREQ remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before the data is sent to the host. The only exception is at the end of DMA transfer when the reception of EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfer, the local CPU and DMA controller has to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of DMACK_N will automatically selects the main endpoint (endpoint 2) regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, DMREQ, DMACK_N and EOT_N are NOT used, instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle, and the destination accessed during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. ENDPOINT DESCRIPTION The PDIUSBD12 endpoints are generic enough to be used by various device classes ranging from Imaging, Printer, Mass Storage and Communication device classes. The PDIUSBD12 endpoints can be configured for 4 modes depending on the "Set Mode" command. The 4 modes are: Mode 0 (Non-ISO Mode): no Isochronous transfer Mode 1 (ISO-OUT Mode): Isochronous output only transfer Mode 2 (ISO-IN Mode): Isochronous input only transfer Mode 3 (ISO-IO Mode): Isochronous input and output transfer 1999 Jan 08 5 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 MODE 0 (NON-ISO MODE): ENDPOINT NUMBER 0 1 2 ENDPOINT INDEX 0 1 2 3 4 5 TRANSFER TYPE Control Out Control In Generic Out Generic In Generic Out Generic In ENDPOINT TYPE Default Generic Generic Generic Generic DIRECTION OUT IN OUT IN OUT IN MAX. PACKET SIZE (BYTES) 16 16 16 16 644 644 MODE 1 (ISO-OUT MODE): ENDPOINT NUMBER 0 1 2 ENDPOINT INDEX 0 1 2 3 4 TRANSFER TYPE Control Out Control In Generic Out Generic In Isochronous Out ENDPOINT TYPE Default Generic Generic Isochronous DIRECTION OUT IN OUT IN OUT MAX. PACKET SIZE (BYTES) 16 16 16 16 1284 MODE 2 (ISO-IN MODE): ENDPOINT NUMBER 0 1 2 ENDPOINT INDEX 0 1 2 3 5 TRANSFER TYPE Control Out Control In Generic Out Generic In Isochronous In ENDPOINT TYPE Default Generic Generic Isochronous DIRECTION OUT IN OUT IN IN MAX. PACKET SIZE (BYTES) 16 16 16 16 1284 MODE 3 (ISO-IO MODE): ENDPOINT NUMBER 0 1 2 ENDPOINT INDEX 0 1 2 3 4 5 TRANSFER TYPE Control Out Control In Generic Out Generic In Isochronous Out Isochronous In ENDPOINT TYPE Default Generic Generic Isochronous Isochronous DIRECTION OUT IN OUT IN OUT IN MAX. PACKET SIZE (BYTES) 16 16 16 16 644 644 NOTES: 1. Generic endpoint can be used either as Bulk or Interrupt endpoint 2. The main endpoint (endpoint number 2) is double-buffered to ease synchronization with the real time applications and to increase throughput. 3. DMA access is for the main endpoint (endpoint number 2) only. 4. Denotes double buffering. The size shown is for a single buffer. MAIN ENDPOINT The main endpoint (endpoint number 2) is special in a few ways. It is the primary endpoint for sinking or sourcing relatively large data. As such, it implements a host of features to ease the task of transferring large data: 1. Double buffering. This allows parallel operation between USB access and local CPU access thus increasing throughput. Buffer switching is handled automatically. This results in transparent buffer operation. 2. Supports for DMA (Direct Memory Access) operation. This can be interleaved with normal I/O operation to other endpoints. 3. Automatic pointer handling during DMA operation. No local CPU intervention is necessary when `crossing' the buffer boundary. 4. Configurable for either isochronous transfer or non-isochronous (bulk and interrupt) transfer. 1999 Jan 08 6 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 PINNING Pin configuration DATA<0> DATA<1> DATA<2> DATA<3> GND DATA<4> DATA<5> DATA<6> DATA<7> 1 2 3 4 5 6 7 8 9 28 A0 27 VOUT3.3 26 D+ 25 D- 24 VDD 23 XTAL2 22 XTAL1 21 GL_N 20 RESET_N 19 EOT_N 18 DMACK_N 17 DMREQ 16 WR_N 15 RD_N ALE 10 CS_N 11 SUSPEND 12 CLKOUT 13 INT_N 14 SV01019 Pin Description PIN 1 2 3 4 5 6 7 8 9 SYMBOL DATA <0> DATA <1> DATA <2> DATA <3> GND DATA <4> DATA <5> DATA <6> DATA <7> TYPE IO2 IO2 IO2 IO2 P IO2 IO2 IO2 IO2 DESCRIPTION Bit 0 of bi-directional data. Slew-rate controlled. Bit 1 of bi-directional data. Slew-rate controlled. Bit 2 of bi-directional data. Slew-rate controlled. Bit 3 of bi-directional data. Slew-rate controlled. Ground. Bit 4 of bi-directional data. Slew-rate controlled. Bit 5 of bi-directional data. Slew-rate controlled. Bit 6 of bi-directional data. Slew-rate controlled. Bit 7 of bi-directional data. Slew-rate controlled. Address Latch Enable. The falling edge is used to close the latch of the address information in a multiplexed address/ data bus. Permanently tied low for separate address/ data bus configuration. Chip Select (Active Low). Device is in Suspend state. Programmable Output Clock (slew-rate controlled). Interrupt (Active Low). 28 A0 I 21 22 23 GL_N XTAL1 XTAL2 OD8 I O 20 RESET_N I PIN 15 16 17 18 SYMBOL RD_N WR_N DMREQ DMACK_N TYPE I I O4 I DESCRIPTION Read Strobe (Active Low). Write Strobe (Active Low). DMA Request. DMA Acknowledge (Active Low). End of DMA Transfer (Active Low). Double up as Vbus sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. Reset (Active Low and asynchronous). Built-in Power-On-Reset circuit present on chip, so pin can be tied HIGH to VCC. GoodLink LED indicator (Active Low) Crystal Connection 1 (6 MHz) Crystal Connection 2 (6 MHz). If external clock signal, instead of crystal, is connected to XTAL1, then XTAL2 should be floated. Voltage supply (4.0 - 5.5V). To operate the IC at 3.3V, supply 3.3V to both VCC and VOUT3.3 pins. USB D- data line USB D+ data line 3.3V regulated output. To operate the IC at 3.3V, supply a 3.3V to both VCC and VOUT3.3 pins Address bit. A0=1 selects command instruction; A0=0 selects the data phase. This bit is a don't care in a multiplexed address and data bus configuration and should be tied high. 19 EOT_N I 10 ALE I 24 VCC P 11 12 13 14 CS_N SUSPEND CLKOUT INT_N I I,OD4 O2 OD4 25 26 27 D- D+ VOUT3.3 A A P NOTE: 1. O2 OD4 OD8 IO2 O4 : Output with 2 mA drive : Output Open Drain with 4 mA drive : Output Open Drain with 8 mA drive : Input and Output with 2 mA drive : Output with 4mA drive 7 1999 Jan 08 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 COMMAND SUMMARY COMMAND NAME Set Address/Enable Set Endpoint Enable Set Mode Set DMA Read Interrupt Register Select Endpoint RECIPIENT Initialization Commands Device Device Device Device Data Flow Commands Device Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Read Last Transaction Status Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Read Buffer Write Buffer Set Endpoint Status Selected Endpoint Selected Endpoint Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 OUT Endpoint 2 IN Acknowledge Setup Clear Buffer Validate Buffer Send Resume Read Current Frame Number Selected Endpoint Selected Endpoint Selected Endpoint General Commands F6h F5h None Read 1 or 2 bytes F4h 00h 01h 02h 03h 04h 05h 40h 41h 42h 43h 44h 45h F0h F0h 40h 41h 42h 43h 44h 45h F1h F2h FAh Read 2 bytes Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte (optional) Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read 1 byte Read n bytes Write n bytes Write 1 byte Write 1 byte Write 1 byte Write 1 byte Write 1 byte Write 1 byte None None None D0h D8h F3h FBh Write 1 byte Write 1 byte Write 2 bytes Write/Read 1 byte CODING DATA PHASE 1999 Jan 08 8 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 COMMAND DESCRIPTION Command Procedure There are three basic types of commands: Initialization, Data Flow and General commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. Configuration Byte 7 0 6 0 5 0 4 0 3 1 2 1 1 1 0 0 POWER ON VALUE RESERVED NO LAZYCLOCK CLOCK RUNNING INTERRUPT MODE SoftConnectTM RESERVED; WRITE 0 Initialization Commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. Set Address / Enable Command Data : D0h : Write 1 byte No LazyClock ENDPOINT CONFIGURATION SV00861 This command is used to set the USB assigned address and enable the function. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POWER ON VALUE ADDRESS ENABLE A `1' indicates that CLKOUT will not switch to LazyClock. A `0' indicates that the CLKOUT switches to LazyClock 1ms after the Suspend pin goes high. LazyClock frequency is 30 kHz 40%. The programmed value will not be changed by a bus reset. A `1' indicates that the internal clocks and PLL are always running even during Suspend state. A `0' indicates that the internal clock, crystal oscillator and PLL are stopped whenever not needed. To meet the strict Suspend current requirement, this bit needs to be set to `0'. The programmed value will not be changed by a bus reset. A `1' indicates that all errors and "NAKing" are reported and will generate an interrupt. A `0' indicates that only OK is reported. The programmed value will not be changed by a bus reset. A `1' indicates that the upstream pull-up resistor will be connected if VBUS is available. A `0' means that the upstream resistor will not be connected. The programmed value will not be changed by a bus reset. These two bits set the endpoint configurations as follows: Mode 0 (Non-ISO Mode) Mode 1 (ISO-OUT Mode) Mode 2 (ISO-IN Mode) Clock Running SV00825 Address Enable The value written becomes the address. A `1' enables this function. Interrupt Mode Set Endpoint Enable Command Data : D8h : Write 1 byte The generic/Isochronous endpoints can only be enabled when the function is enabled via the Set Address/Enable command. SoftConnectTM 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 POWER ON VALUE GENERIC/ISOCHRONOUS ENDPOINTS RESERVED; WRITE 0 Endpoint configuration SV00860 Generic/Isochronous Endpoint A value of `1' indicates the generic/isochronous endpoints are enabled. Mode 3 (ISO-IO Mode) See Endpoint Description for more details. Set Mode Command Data : F3h : Write 2 bytes The Set Mode command is followed by two data writes. The first byte contains the configuration byte values. The second byte is the clock division factor byte. 1999 Jan 08 9 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 Clock Division Factor Byte 76 00 5 X 4 X 3 1 2 0 1 1 0 1 7 0 POWER ON VALUE CLOCK DIVISION FACTOR RESERVED SET_TO_ONE SOF-ONLY interrupt mode 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POWER ON VALUE DMA BURST DMA ENABLE DMA DIRECTION AUTO RELOAD INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE ENDPOINT INDEX 5 INTERRUPT ENABLE SV00862 Clock Division Factor The value indicates clock division factor for CLKOUT. The output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up (or down) by the user. The minimum value is one giving the range of frequency from 4 to 24 MHz. The minimum value of N is ZERO giving a maximum frequency of 48 MHz. The maximum value of N is ELEVEN giving a minimum frequency of 4 MHz. The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. This bit needs to be set to 1 prior to any DMA read or DMA write operation. This bit should always be set to 1 after power. It is zero after power-on reset. Setting this bit to 1 will cause the interrupt line to be interrupted due to Start of Frame clock (SOF) ONLY, regardless of the setting of pin-interrupt mode, bit 5 of setDMA. SV00863 DMA Burst Selects the burst length for DMA operation: 00 01 10 11 Single cycle DMA Burst (4 cycle) DMA Burst (8 cycle) DMA Burst (16 cycle) DMA DMA Enable SET_TO_ONE SOF-ONLY interrupt mode Writing a `1' to this bit will start DMA operation through the assertion of DMREQ. The main endpoint buffer needs to be full (for DMA Read) or empty (for DMA Write) before DMREQ will be asserted. In a single cycle DMA mode, the DMREQ is deactivated upon receiving DMACK_N. In burst mode DMA, the DMREQ is deactivated after the number of burst is exhausted. It is then asserted again for the next burst. This process continues until EOT_N is asserted together with DMACK_N and either RD_N or WR_N which will reset this bit to `0' and terminate the DMA operation. The DMA operation can also be terminated by writing a `0' to this bit. This bit determines the direction of data flow during a DMA transfer. A `1' means external shared memory to PDIUSBD12 (DMA Write); a `0' means PDIUSBD12 to the external shared memory (DMA Read). When this bit is set to `1', the DMA operation will automatically restart. A `0' signifies a normal interrupt pin mode where interrupt is generated as a logical OR of all the bits in the interrupt registers. A `1' signifies that the interrupt will occur when Start of Frame clock (SOF) is seen on the upstream USB bus. The other normal interrupts are still active. A `1' allows for interrupt to be generated whenever the endpoint buffer contains a valid packet. Normally turned off for DMA operation to reduce unnecessary CPU servicing. A `1' allows for interrupt to be generated whenever the endpoint buffer is validated (see the Validate Buffer command). Normally turned off for DMA operation to reduce unnecessary CPU servicing. DMA Direction Set DMA Command Data : FBh : Read/Write 1 byte Auto Reload Interrupt Pin Mode The set DMA command is followed by one data write/read to/from the DMA configuration register. DMA Configuration register During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operation, the header will be skipped by the PDIUSBD12. See Read Buffer command. For DMA write operation, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. Endpoint Index 4 Interrupt Enable Endpoint Index 5 Interrupt Enable 1999 Jan 08 10 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 INTERRUPT MODES Bit 7 of Clock Division Factor SOF_ONLY interrupt mode 0 0 1 Bit 5 of SetDMA INTERRUPT_PIN mode 0 1 X Types of Interrupt Normal Interrupt1 Normal Interrupt + SOF1 SOF interrupt ONLY Interrupt Register Byte 2 This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 POWER ON VALUE DMA EOT RESERVED NOTE: 1. Normal Interrupt: Normal interrupts from Interrupt Register : Data Flow Commands Data flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data. Bus Reset SV00865 Read Interrupt Register Command Data : F4h : Read 2 bytes Suspend Change Interrupt Register Byte 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 After a bus reset an interrupt will be generated this bit will be `1'. A bus reset is identical to a hardware reset through the RESET_N pin with the exception that a bus reset generates an interrupt notification and the device is enabled at default address 0. When the PDIUSBD12 did not receive 3 SOFs, it will go into suspend state and the Suspend Change bit will be high. Any change to the suspend or awake state will set this bit high and generate an interrupt. This bit signifies that DMA operation is completed. POWER ON VALUE CONTROL OUT ENDPOINT CONTROL IN ENDPOINT ENDPOINT 1 OUT ENDPOINT 1 IN MAIN OUT ENDPOINT MAIN IN ENDPOINT BUS RESET SUSPEND CHANGE DMA EOT Select Endpoint Command Data : 00-05h : Optional Read 1 byte SV00864 The Select Endpoint command initializes an internal pointer to the start of the Selected buffer. Optionally, this command can be followed by a data read, which returns this byte. 7 X 6 X 5 X 4 X 3 X 2 X 1 0 0 0 POWER ON VALUE FULL/EMPTY STALL RESERVED SV00866 Full/Empty Stall A `1' indicates the buffer is full, `0' indicates an empty buffer. A `1' indicates the selected endpoint is in the stall state. 1999 Jan 08 11 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 Read Last Transaction Status Register Command Data : 40-45h : Read 1 byte ERROR CODES ERROR CODE 0000 0001 0010 0011 0100 0101 No Error PID encoding Error; bits 7-4 are not the inversion of bits 3-0 PID unknown; encoding is valid, but PID does not exist Unexpected packet; packet is not of the type expected (= token, data or acknowledge), or SETUP token to a non-control endpoint Token CRC Error Data CRC Error Time Out Error Never happens Unexpected End-of-packet Sent or received NAK Sent Stall, a token was received, but the endpoint was stalled Overflow Error, the received packet was longer than the available buffer space Bitstuff Error Wrong DATA PID; the received DATA PID was not the expected one RESULT The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read. This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction. 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POWER ON VALUE DATA RECEIVE/TRANSMIT SUCCESS ERROR CODE (SEE TABLE) SETUP PACKET DATA 0/1 PACKET PREVIOUS STATUS NOT READ 0110 0111 1000 1001 1010 SV00867 1011 1101 Data Receive/Transmit Success Error Code Setup Packet A `1' indicates data has been received or transmitted successfully. See Table below, Error Codes. A `1' indicates the last successful received packet had a SETUP token (this will always read `0' for IN buffers). A `1' indicates the last successful received or sent packet had a DATA1 PID. A `1' indicates a second event occurred before the previous status was read. 1111 Read Buffer Command Data : F0h : Read multiple bytes (max 130) Data 0/1 Packet Previous Status not Read The Read Buffer command is followed by a number of data reads, which return the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1. The buffer pointer is not reset to the buffer start by the Read Buffer command. This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint). The data in the buffer are organized as follows: byte 0: byte 1: byte 2: byte 3: ...... The first two bytes will be skipped in the DMA read operation. Thus, the first read will get Data Byte 1, the second read will get Data Byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. Reserved: can have any value Number/length of data bytes Data byte 1 Data byte 2 1999 Jan 08 12 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 Write Buffer Command Data : F0h : Write multiple bytes (max 130) STALLED RESERVED 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 0 POWER ON VALUE The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be `0'. During DMA write operation, the first two bytes will be bypassed. Thus, the first write will write into Data Byte 1, the second write will write into Data Byte 2, etc. For non-isochronous transfer (bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host. WARNING: There is no protection against writing or reading over a buffer's boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data in an OUT buffer are only meaningful after a successful transaction. The exception is during DMA operation on the main endpoint (endpoint 2); in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). SV00871 Stalled A `1' indicates the endpoint is stalled. Acknowledge Setup Command Data : F1h : None The arrival of a SETUP packet flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for both IN and OUT endpoints. The microcontroller needs to re-enable these commands by the Acknowledge Setup command. This ensures that the last SETUP packet stays in the buffer and no packet can be sent back to the host until the microcontroller has acknowledged explicitly that it has seen the SETUP packet. The microcontroller must send the Acknowledge Setup command to both the IN and OUT endpoints. Clear Buffer Command Data : F2h : None GENERAL COMMANDS Send Resume Command Data : F6h : None When a packet is received completely, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the buffer is cleared, new packets will be accepted. Validate Buffer Command Data : FAh : None Sends an upstream resume signal for 10 ms. This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write. When the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. Read Current Frame Number Command Data : F5h : Read One or Two Bytes Set Endpoint Status Command Data : 40-45h : Write 1 byte This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant Byte first. A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it. When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID. Even when unstalled, writing Set Endpoint Status to `0' initializes the endpoint. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X LEAST SIGNIFICANT BYTE 7 0 6 0 5 0 4 0 3 0 2 X 1 X 0 X MOST SIGNIFICANT BYTE SV00869 1999 Jan 08 13 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC1 VCC2 VI VI/O VAI/O VO Tamb PARAMETER DC supply voltage (Main mode) DC supply voltage (Alternate mode) DC input voltage range DC input voltage range for I/O DC input voltage range for analog I/O DC output voltage range Operating ambient temperature range in free air See DC and AC characteristics per device TEST CONDITIONS Apply VCC1 to VCC pin only Apply VCC2 to both VCC and Vout3.3 pins MIN 3.6 3.0 0 0 0 0 -40 MAX 5.5 3.6 5.5 5.5 3.6 VCC 85 UNIT V V V V V V C DC CHARACTERISTICS (Digital pins) SYMBOL Input Levels VIL VIH PARAMETER LOW level input voltage HIGH level input voltage Hysteresis voltage TEST CONDITIONS MIN TYP MAX 0.8 UNIT V V V V V V V 2.0 ST (Schmitt Trigger) pins IOL = rated drive IOL = 20 A IOH = rated drive IOH = 20 A OD (Open Drain) pins Oscillator stopped and inputs to GND/VCC 15 2.4 VCC - 0.1 5 5 15 0.4 0.7 0.4 0.1 VHYS Output Levels VOL VOH LOW level out ut voltage output HIGH level output voltage out ut Leakage Current IOZ IL IS IO OFF state current Input leakage current Suspend current Operating current A A A mA DC CHARACTERISTICS (AI/O pins) SYMBOL Leakage Current ILO Input Levels VDI VCM VSE Output Levels VOL VOH Capacitance CIN ZDRV1 ZPU Transceiver capacitance Driver output resistance Pull-up resistance Pin to GND Steady state drive SoftConnectTM = ON 29 1.1 20 44 1.9 pF k Output Resistance Pull-up Resistance NOTE: 1. Includes external resistors of 18 1% each on D+ and D-. Static output LOW Static output HIGH RL of 1.5k to 3.6V RL of 15k to GND 2.8 0.3 3.6 V V Differential input sensitivity Differential common mode range Single-ended receiver threshold |(D+) - (D-)| Includes VDI range 0.2 0.8 0.8 2.5 2.0 V V V Hi-Z state data line leakage 0V < VIN < 3.3V 10 A PARAMETER TEST CONDITIONS MIN MAX UNIT 1999 Jan 08 14 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 LOAD FOR D+/D- 1.5k IS INTERNAL TEST POINT 22 D. U. T. 15k CL = 50pF SV00849 AC CHARACTERISTICS (AI/O pins, FULL speed) SYMBOL Driver characteristics Transition Time: Rise time Fall time Rise/fall time matching Output signal crossover voltage Source EOP width Differential data to EOP transition skew Receiver Data Jitter Tolerance To next transition For paired transitions EOP Width at Receiver Must reject as EOP Must accept Figure 1 Figure 1 PARAMETER TEST CONDITIONS CL = 50pF; Rpu = 1.5k on D+ to VCC Between 10% and 90% (tr/tf) 4 4 90 1.3 160 -2 20 20 110 2.0 175 5 ns ns % V ns ns MIN MAX UNIT tr tf tRFM VCRS Driver Timings tEOPT tDEOP Receiver Timings: tJR1 tJR2 tEOPR1 tEOPR2 Characterized but not implemented as production test. Guaranteed b d i G t d by design. Figure 1 -18.5 -9 40 82 18.5 9 ns ns ns ns tPERIOD CROSSOVER POINT EXTENDED CROSSOVER POINT DIFFERENTIAL DATA LINES SOURCE EOP WIDTH: tEOPT DIFFERENTIAL DATA TO SEO/EOP SKEW N * tPERIOD + tDEOP RECEIVER EOP WIDTH: tEOPR1, tEOPR2 SV00837 Figure 1. Differential data to EOP transition skew and EOP width 1999 Jan 08 15 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 AC CHARACTERISTICS (Parallel Interface) SYMBOL ALE Timings tLH tAVLL tLLAX tCLWL tWHCH tAVWL tWHAX tWL tWDSU tWDH tWC ALE High pulse width Address Valid to ALE Low time ALE Low to Address transition time CS_N (DMACK_N) Low to WR_N Low time WR_N High to CS_N (DMACK_N) High time A0 Valid to WR N Low time WR_N WR_N High to A0 transition time WR_N Low pulse width Write Data Setup time Write Data Hold time Write Cycle time 01 5 01 1302 5 20 30 10 500 01 1302 5 01 20 20 20 500 20 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PARAMETER TEST CONDITIONS MIN MAX UNIT Write Timings Read Timings tC CLRL tRHCH tAVRL tRL tRLDD tRHDZ tRC CS_N (DMACK_N) CS N (DMACK N) Low to RD N Low time RD_N RD_N High to CS_N (DMACK_N) High time A0 Valid to RD_N Low time RD_N Low pulse width RD_N Low to Data Driven time RD_N High to Data Hi-Z time Read Cycle time NOTES: 1. Can be negative. 2. For DMA access only on the Modulo 64th byte and the Second Last (EOT-1) byte. tLH ALE tAVLL tLLAX DATA[7:0] ADDRESS DATA SV00872 Figure 2. ALE Timing 1999 Jan 08 16 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 tCLRL tCLWL CS_N DMACK_N tAVRL tAVWL A0 COMMAND = 1, DATA = 0 tRHCH tWHCH tWHAX tWL WR_N tWC tWDSU tWDH DATA[7:0] VALID DATA tRL RD_N tRHNDV tRLDD tRHDZ tRC DATA[7:0] VALID DATA tRLDD VALID DATA SV00873 Figure 3. Parallel Interface TIming (I/O and DMA) AC CHARACTERISTICS (DMA) SYMBOL Single-cycle DMA Timings tAHRH tSHAH tRHSH tEL DMACK_N High to DMREQ High time RD_N/WR_N High to DMACK_N High time DMREQ High to RD_N/WR_N High time EOT_N Low Pulse Width (Simultaneous DMACK_N, RD_N/WR_N and EOT_N low time) 130 120 10 330 ns ns ns ns PARAMETER TEST CONDITIONS MIN MAX UNIT Burst DMA Timings tSLRL tRHNDV tELRL RD_N/WR_N Low to DMREQ Low time RD_N (only) High to next data valid EOT_N Low to DMREQ Low time 40 420 40 ns ns ns EOT Timings 1999 Jan 08 17 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 tRHSH tAHRH DMREQ tSHAH DMACK_N RD_N/WR_N EOT_N tEL NOTES: EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW. tALRL timing starts from the DMACK_N or RD_N/RW_N depending which goes LOW later. Figure 4. Single-cycle DMA Timing SV00874 tRHSH DMREQ tSLRL DMACK_N tSHAH RD_N/WR_N SV00875 Figure 5. Burst DMA Timing DMREQ tELRL DMACK_N RD_N/WR_N EOT_N SV00876 Figure 6. DMA Terminated by EOT 1999 Jan 08 18 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 1999 Jan 08 19 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 SO28: plastic small outline package; 28 leads; body width 7.5mm SOT136-1 1999 Jan 08 20 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 NOTES 1999 Jan 08 21 Philips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 01-99 Document order number: 9397 750 04979 Philips Semiconductors yyyy mmm dd 22 |
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